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ADS-325A
10-Bit, 20MHz Sampling A/D Converter
IN N O VA T IO N a n d E X C E L L E N C E
FEATURES
* * * * * * * * * * * 10-bit, 20MHz sampling 1LSB max. differential nonlinearity Internal calibration circuit Internal S/H amplifier 70MHz input bandwidth TTL/CMOS compatible in-out logic Latched three-state output data Single +5V supply Low 150mW power dissipation Small 48 pin LQFP package Low cost
INPUT/OUTPUT CONNECTIONS
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FUNCTION
BIT 10 (LSB) BIT 9 BIT 8 BIT 7 BIT 6 DIGITAL GROUND (DGND) +DVS (Digital) BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) TEST PIN TEST SIGNAL IN RESET DIGITAL GROUND (DGND) SELECT (SEL) +AVS (Analog) TEST MODE LINV MINV A/D CLOCK OUTPUT ENABLE (OE) CHIP ENABLE (CE)
PIN
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
FUNCTION
DIGITAL GROUND (DGND) NO CONNECTION NO CONNECTION +DVS (Digital) ANALOG GROUND (AGND) ANALOG GROUND (AGND) TEST SIGNAL IN CALIBRATION (CAL) NO CONNECTION ANALOG INPUT (VIN) TEST SIGNAL OUT TEST SIGNAL IN ANALOG GROUND (AGND) REFERENCE BOTTOM (VRB) REFERENCE BOTTOM (VRB) NO CONNECTION NO CONNECTION NO CONNECTION REFERENCE TOP (VRT) REFERENCE TOP (VRT) ANALOG GROUND (AGND) ANALOG GROUND (AGND) +AVS (Analog) +AVS (Analog)
GENERAL DESCRIPTION
DATEL's ADS-325A is a low power, 10-bit, 20MHz, CMOS sampling A/D converter. Its small 48 pin plastic LQFP package contains a S/H amplifier, a 3-state output register, linearity calibration circuitry, and all necessary control logic. Only two external reference voltages, an A/D clock and a few digital inputs are required. The A/D clock may be applied with 50% duty cycle. The excellent dynamic performance includes a spurious free dynamic range of 65dB and a signal-to-noise ratio with distortion of 54dB with a 3MHz input. ADS-325A is capable of operating from a single +5V power supply and typically consumes only 150mW. It can also operate from a +5V analog VS with +3.3V digital VS enabling an interface with 3.3V logic circuitry. The ADS-325A is ideally suited for high quality video/ CCD imaging applications.
AGND
+AVS
44 43 27 28 36 18 25 26
SENSE AMP #1
12 BIT 1 (MSB) COARSE CORRECTION AND LATCH 11 BIT 2 10 BIT 3 9 BIT 4 8 BIT 5
VIN 39 VRT 29 VRT 30
S/H AMP
+
x8
5 BIT 6 COARSE COMPARISON AND ENCODE DAC FINE COMPARISON AND ENCODE 4 BIT 7 FINE LATCH 3 BIT 8 2 BIT 9 1 BIT 10 (LSB) SENSE AMP #2 21 MINV 20 LINV 19 TEST MODE
VRB 34 VRB 35
CALIBRATION UNIT
A/D CLOCK 22 CE 24 OE 23
TIMING GEN.
AUTOCALIBRATION PULSE GENERATOR
41 CAL 17 SEL 15 RESET
Figure 1. ADS-325A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 * Email: sales@datel.com * Internet: www.datel.com
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ABSOLUTE MAXIMUM RATINGS (TA = +25C)
PARAMETERS Supply Voltages (+AVS and +DVS ) Reference Voltage (VRT and VRB) Input Voltage, Analog (VIN) Input Voltage, Digital (VIH and VIL) Output Voltage, Digital (VOH and VOL) LIMITS 0 to +7 -0.5 to +AVS +0.5 -0.5 to +AVS +0.5 -0.5 to +AVS +0.5 -0.5 to +DVS +0.5 UNITS Volts Volts Volts Volts Volts PERFORMANCE (CONT.) Spurious Free Dynamic Range fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 7MHz fIN = 10MHz POWER REQUIREMENTS MIN. -- -- -- -- -- -- TYP. 60 59 60 65 50 49 MAX. -- -- -- -- -- -- UNITS dB dB dB dB dB dB
FUNCTIONAL SPECIFICATIONS
(Typical at fS = 20MHz, +AVS = +5V, +DVS = +3.3V, VRB = +2.0V, VRT = +4.0V, and TA = +25C unless otherwise specified.)
ANALOG INPUTS Input Voltage Range, VIN Input Current VIN = +4V VIN = +2V Capacitance, CIN Bandwidth (-1dB) REFERENCE Reference Input Voltage VRT VRB Input Current IRT IRB Offset Voltage VRT VRB Resistance (VRT - VRB) DIGITAL INPUTS Input Voltage VIH, Logic "1" VIL, Logic "0" Input Current IIH, Logic Loading "1" IIL, Logic Loading "0" A/D Clock Pulse Width TPW1 TPW0 DIGITAL OUTPUTS Output Logic Current IOH, Logic "1" IOL, Logic "0" Leak Current at OE = "1" 3-State Enable Time, TPZE 3-State Disable Time, TPEZ Data Delay, TDL (CL = 20pF) PERFORMANCE Resolution Max. Throughput Rate Min. Throughput Rate Integral Linearity Error Differential Linearity Error Differential Gain Error Differential Phase Error Aperture Delay, Tsd SNR & Distortion fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 7MHz fIN = 10MHz 10 20 -- -- -- -- -- 2 -- -- -- -- -- -- -- -- -- 1.3 0.5 1.0 0.3 4 53 52 53 54 47 45 -- -- 0.5 2 1 -- -- 6 -- -- -- -- -- -- Bits MHz MHz LSB LSB % Degrees ns dB dB dB dB dB dB -3.5 3.5 -- 10 20 8 -- -- -- 15 25 13 -- -- 1 20 30 18 mA mA A ns ns ns +2.3 -- -- -- 25 25 -- -- -- -- -- -- -- +0.8 5 5 -- -- Volts Volts A A ns ns -- +1.8 5 -11 +40 -120 180 +4 +2 7 -7 +90 -70 280 +4.6 -- 11 -5 +140 -20 380 Volts Volts mA mA mV mV MIN. TYP. +2 to +4 -- -50 -- -- 40 -40 9 70 50 -- -- -- MAX. UNITS Volts A A pF MHz
Power Supply Voltage +AVS +DVS |DGND - AGND | Supply Current Analog, +AIS Digital, +DIS Standby Current (CE = "1") Analog, +AIS Digital, +DIS Power Dissipation PHYSICAL/ENVIRONMENTAL Operating Temperature Range Storage Temperature Range Weight Package Footnotes: +DVS = Max., VIH = +DVS +DVS = Max., VIL = 0V OE = AGND, +DVS = Min., VOH = +DVS-0.5V OE = AGND, +DVS = Min., VOL = 0.4V
+4.75 +3.0 -- 20 -- -- -- --
+5.0 -- -- 27 3 -- -- 150
+5.25 +5.25 100 34 5 1 1 --
Volts Volts mV mA mA mA A mW
-20 -55
-- +75 -- +150 0.2 grams 48-pin plastic LQFP
C C
OE = +AVS, +DVS = Max., VOH = +DVS, and VOL = 0V Hi-Z to Active, asynchronous with clock. Active to Hi-Z, asynchronous with clock. Fin = 1kHz NTSC 401RE mod. ramp, fc = 14.3MHz
TECHNICAL NOTES
1. Caution to ESD: Since the ADS-325A is a CMOS device, precautions against static electricity should be taken. 2. +AVS and +DVS: While the unit has separate pins for both the analog supply (+AVS) and the digital supply (+DVS), a time skew between supplying (or removing) both +AVS and +DVS may cause a latch-up problem. DATEL recommends using a common power supply for both +AVS and +DVS to avoid latch-up conditions. It is possible to use +3.3V for +DVS along with +5V for +AVS. Compared to the singe +5V supply application, there will be no significant difference in performance. However, special care should be taken to minimize the time skew between +AVS and +DVS when turning on/off. 3. PC board layout: To obtain fully specified performance careful attention to PC board layout is required. Place large ground planes on the board and connect both analog and digital grounds at one point right beneath the converter. In the case where the grounds are tied at a location distant from the converter, the voltage difference between the grounds must be within 100mV. Tie all ground pins directly to the appropriate ground plane beneath the converter. Bypass +AVS and +DVS pins to ground using 10F tantalum capacitors in parallel with 0.1F ceramic capacitors at locations as close to the unit as possible. 4. Reference Input: Two external voltage references are required for the two reference inputs VRT (pin 29, 30) and VRB (pin 34, 35). Typically, these are +4V for VRT and +2V
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for VRB, which give an analog input range of +2V to +4V. The reference voltages must be within the following limitations: +AVS - 0.4V > = VRT > VRB >= +1.8V, and VRT - VRB > =1.8V Stability of the reference will directly affect the accuracy of the A/D conversion. In this sense, the reference sources must be capable of driving more than 10mA. Also, the VRT and VRB pins should be bypassed to analog ground with 0.1F ceramic capacitors placed as close to the pins as possible. 5. Analog Input: ADS-325A has a broad input bandwidth of 70MHz (@-1dB) with only 9pF of input capacitance at its analog input. The analog input should be driven by a high speed buffer amplifier with sufficient current drive. 6. Digital Inputs: All digital input pins including A/D clock input are CMOS compatible. Each of these pins has an internal overvoltage protection circuit with diodes as shown in Figure 2 (Equivalent circuit diagrams). 7. Control Logic Inputs: ADS-325A has several control logic input pins. Functions of these pins are described in the following: TEST MODE (pin 19), MINV (pin 21), LINV (pin 20) These three pins select the output data format. With a combination of these input states the output data takes any form of binary, complementary binary, 2's compliment, or certain test pattern. Refer to Table 1 (Output coding) and Table 2 (Truth table). CE (Chip Enable, pin 24) For normal operation the input to this pin should be logic low. Input high applied to the pin puts the unit into standby mode. In standby mode the unit dissipates only a few milliwatts or less. OE (Output Enable, pin 23) Input logic low applied to this pin enables the three-state output bits (Bit 1 to Bit 10). Input high disables the outputs. RESET (pin 15) This pin can be used to re-initiate start-up calibration. Normally connect this pin to logic high. See Calibration Function for more details. CAL (Calibration Input, pin 41) This pin is the input for an external calibration pulse. See Calibration Function for more details. SEL (Select, pin 17) Applying logic high to this pin allows use of the internal auto calibration function and blocks out the external pulse from the CAL input. Inputting logic low to the pin disables the internal cal function and allows usage of the external cal pulses. 8. Test IN/OUT pins: Test signal input/output pins are used in the production process. The test signal output pins (pin 13, 38) should normally be left open. Tie the test signal input pin 42 to +AVS and the pins 14 and 37 to +AVS or AGND. 9. Three-state output buffer: A/D output buffer (BIT 1 to BIT 10) is a three-state register controlled by the OE pin. The output logic high level is dependent on +DVS.
+DVS +AVS
39 VIN
OUTPUT BIT
AGND
DGND
Analog Signal Input
+AVS
Digital Data Outputs
+AVS
29 30 VRT
RESET 15 SELECT 17 TEST MODE 19 LINV 20 MINV 21 CLOCK 22 OUTPUT ENABLE (OE) 23 CHIP ENABLE (CE) 24 CAL. PULSE IN (CAL) 41 AGND AGND 34 35 +AVS AGND
VRB
SEL, CLK, CAL, RESET, OE, CE, Test Mode, LINV and MINV Inputs Figure 2. Equivelant Circuits
Reference Input
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CALIBRATION FUNCTION
To achieve its superior linearity ADS-325A has an internal calibration circuit with a built-in calibration pulse generation circuit and an input pin for an external calibration pulse. The calibration circuit consists of three D/A converters, a pattern generator and an averaging circuit. With either internal or external calibration pulses applied to the calibration circuit, the circuit senses an offset of the x8 gain amplifier and two reference biases supplied from the VRT and the VRB to a fine comparator/encoder block, and compensates them using the three DACs. With a single negative going calibration pulse a unit cycle of calibration is completed. It is initiated with the negative going edge of the calibration pulse and takes seven A/D clock periods to be completed. Due to the fact that this calibration cycle occupies the lower comparator for four A/D clock periods the lower five bits of the output data remain constant through 4 clock cycles after the completion of the cycle. Figure 3 shows the timing for the calibration cycle. A sequence of seven unit calibration cycles initiated by seven calibration pulses, completes a single calibration process. The number of calibration processes required depends on the condition of the device and on the stability of the references and the power. Even in worst case, 80 calibration processes done by 560 calibration pulses are enough to finish the whole calibration. There are three modes of the calibration function. These are: a. Start-up calibration function b. Internal auto-calibration function c. External calibration function
Table 1. Digital Output Coding
For operation in modes a. and b. the ADS-325A has a built-in calibration pulse generation circuit. Figure 4a. illustrates a simplified block diagram of this circuit. Start-up Calibration Function At power-up of the unit the initial calibration process requires over 600 calibration pulses. The internal start-up calibration function automatically generates these pulses when power is first applied to the ADS-325A. To initiate the start-up calibration, the following five conditions must be met. See Figure 4b. 1. The supply voltage +AVS must be at least 2.5 Volts higher than AGND. 2. The voltage difference between VRT and VRB must be at least 1 Volt. 3. The RESET pin (pin 15) must be set high. 4. The CE pin (pin 24) must be set low. 5. Condition 1 must be met before condition 2. Once all of the above conditions have been met, the calibration pulses are generated by counting 16 A/D clock cycles on a 14-bit counter until closing the gate when the carry-out occurs. The time required for the start-up calibration is determined by the following formula: Start-up Calibration Time = 1/fCLK x 16 x 16,384 where fCLK is the frequency of the A/D clock input. For example, a clock frequency of 14.3MHz requires a calibration time of 18.3ms.
Table 2. Digital Output Truth Table
TEST MODE = 1, LINV = 0, MINV = 0 Analog Input Voltage
3.998V 3.996V : 3.000V 2.998V : 2.002V 2.000V
P = Positive True; N = Negative True (inverted) TEST MODE LINV
1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0
Step
1023 1022 : 512 511 : 1 0
Digital Output Code MSB LSB
11 11 10 01 00 00 1111 1111 : 0000 1111 : 0000 0000 1111 1110 0000 1111 0001 0000
MINV
0 0 1 1 1 1 0 0
MSB
PP PN NP NN 10 11 00 01
Digital Output LSB
PPPP NNNN PPPP NNNN 1010 0101 1010 0101 PPPP NNNN PPPP NNNN 1010 0101 1010 0101
7 Clock Cycles
A/D CLOCK
> 10ns
CAL
>1 Clock Cycle
BIT 1 TO BIT 5 (MSB) BIT 6 TO BIT 10 (LSB)
N-3 N-2 N-1
N
N+1 N+2 N+3 N+4 N+5
N-3 N-2 N-1
N
N+5
4 Clock Cycles
Figure 3. Calibration Timing Diagram
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Re-initiating the Start-up Calibration The start-up calibration function can be re-initiated at any time desired after the power and the references are supplied. Apply a positive pulse to CE pin (pin 24) or a negative pulse to RESET pin (pin 15). The pulse width of these pulses must be equal to or wider than one A/D clock cycle. Also due to this feature, you can make sure of a proper start-up calibration at power-up by making a C-R delay connection with the RESET pin as shown in Figure 4c. Using Start-up Calibration Function Only Internal and external calibration functions need not be employed after start-up calibration. To use only the start-up calibration function, connect the SEL pin (pin 17) to AGND and the CAL pin (pin 14) to +AVS or AGND. Auto Calibration Function After the start up calibration is completed, the internal calibration function can periodically and automatically generate calibration pulses when the auto calibration mode is enabled. To enable this function connect the SEL pin (pin 17) and the CAL pin (pin 41) to +AVS. In this mode a 24-bit counter is counted with every 16 A/D clock cycles and the carry-out is used as the calibration pulse. The period of the calibration pulse generated is as follows: Period of Auto-calibration pulse = 1/fCLK x 16 x 16,777,216 For the case when the A/D clock frequency is 14.3MHz, the calibration pulse generation cycle is 18.8 seconds. Since a single calibration process is performed once every seven pulses, the total calibration cycle is approximately 132 seconds.
OUT
+AVS
14-BIT COUNTER A/D CLOCK 1/16 CLR CO
D
Q
CLR
+AVS AGND
SENSE AMP #1
24-BIT COUNTER CO CLR
VRT VRB RESET CE
SENSE AMP #2 SEL CAL
Figure 4a Internal Calibration Pulse Generation Circuit
VOLTS
+5 +AVS VRT 1V +2.5 VRB
+AVS +AVS 5V VRT
TIME
0
RESET 15
SENSE AMP #1
VRB
SENSE AMP #2 CLR RESET = HIGH, CE = LOW
CE = "L"
Figure 4b. Conditions for Start-Up Calibration
Figure 4c. Start-up Calibration using RESET
T PW1
T PW0
CLOCK
+1.65V
Tsd ANALOG INPUT N
N+1 N+2 +1.65V (+DVS = +3.3V) +2.5V (+DVS = +5.0V) N+3 TDL N+4 OUTPUT ENABLE (OE) OUTPUT DATA
TPEZ
TPZE +1.65V (+DVS = +3.3V) +2.5V (+DVS = +5.0V)
OUTPUT DATA
N-3
N-2
N-1
N
ACTIVE
HIGH IMPEDENCE
ACTIVE
= SAMPLING POINT +1.65V (+DVS = +3.3V) +2.5V (+DVS = +5.0V)
Figure 5. ADS-325A Timing Diagrams
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As stated before, the five lower bits of the output data will remain constant for 4 clock cycles with every generation of the calibration pulse. Since the auto calibration pulses are generated asynchronously, this may create problems in certain applications. External Calibration Function To avoid the asynchronous data fixation due to the calibration process, you can disable the internal auto calibration function and use an external calibration pulse which is synchronized with the analog input. Input the external calibration pulse to the CAL pin (pin 14) and tie the SEL pin (pin 17) to AGND. When digitizing a video signal, for example, you can synchronize the external calibration pulses with the V-sync or H-sync cycles of the video signal to avoid losing any data during the video signal cycles. See figure 6a. and 6b.
ANALOG INPUT A/D CLOCK RESET CAL
Figure 6a. Applying CAL Pulse Every H Sync.
ANALOG INPUT A/D CLOCK RESET CAL
Figure 6b. Applying CAL Pulse Every V Sync.
+AVS 10F + VRT (+4V)
0.1F
0.1F 0.1F
0.1F
VRB (+2V)
0.1F
NOTES: 1. For using Start-up calibration and External CAL Pulse Mode, close JP1 and JP4, and open JP2 and JP3. 2. For using Start-up calibration and Internal Auto-calibration Mode, close JP2 and JP3, and open JP1 and JP3. 3. For using Start-up calibration Mode only, close JP2 and JP4, and open JP1 and JP3.
+AVS
36 37 38
35 34 VRB
33
32
31 30 VRT
29
28 27 AGND
26 25 CE 24 OE 23 CLK 22 MINV 21 LINV 20
ANALOG IN (+2V to +4V) EXT. CAL. PULSE IN
JP1
39 VIN 40 41 CAL
A/D CLOCK IN
JP2
42 43 AGND 44
ADS-325A
MODE 19
JP3
+AVS 18 SEL 17
0.1F
45 +DVS 46 47 48 DGND 1 2 3 4 5 6 7 8 9 10 11 13 12 DGND 16 RESET 15
JP4 JP5 10F + JP6 0.1F RESET IN
4. RESET pin (Pin 15) should normally be connected to +AVS (close JP5). To re-initiate the start-up calibration after power-up, close JP6 to apply external RESET pulse.
0.1F BIT 10 (LSB) BIT 1 (MSB)
Figure 7. Typical ADS-325A Connection Diagram
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Supply Current vs. Ambient Temperature Maximum Operating Frequency (MHz) Maximum Operating Frequency vs. Ambient Temperature Output Data Delay vs. Ambient Temperature
29 Supply Current (mA) fc = 20MHz fin = 1kHz ramp 28
35 fin = 1kHz ramp 30 Output Data Delay (ns)
17 fc = 1MHz CL = 20pF 15
25
27
13
20
-20
0
25
50
75
-20
0
25
50
75
-20
0
25
50
75
Ambient Temperature (C)
Ambient Temperature (C)
Ambient Temperature (C)
Sampling Delay vs. Ambient Temperature
SNR vs. Input Frequency SFDR (Spurious Free Dynamic Range) (dB)
SFDR vs. Input Frequency
fc = 1MHz Sampling Delay (ns)
SNR (Signal to Noise Ratio) (dB)
6
60
60
4
50
50
2
40 fc = 20MHz Vin = 2Vp-p Ta = +25C 100k 1M 10M
40 fc = 20MHz Vin = 2Vp-p Ta = +25C 100k 1M 10M
-20
0
25
50
75
Ambient Temperature (C)
Input Frequency (Hz)
Input Frequency (Hz)
ENOB vs. Input Frequency ENOB (Effective number of bits) (BITS)
Analog Input Bandwidth
9
1 0
8
Gain (dB) fc = 20MHz Vin = 2Vp-p Ta = +25C 100k 1M 10M
-1 -2 -3 fc = 20MHz Vin = 2Vp-p Ta = +25C 100k 1M 10M
7
Input Frequency (Hz)
Input Frequency (Hz)
Figure 8. Typical Performance Curves
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MECHANICAL DIMENSIONS
A B
C
D
F
E
H
I K
G
J
ORDERING INFORMATION
Model Number ADS-325A Bits/Throughput Rate 10 Bits/20MHz Package 48-pin, plastic LQFP
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ISO 9001
R E G I S T E R E D
DS-0297A 03/98
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com Data Sheet Fax Back: (508) 261-2857
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

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